1. Field of the Invention
The invention relates to a writing circuit for a phase change memory, and more particularly to a fast writing circuit for a phase change memory with one current source.
2. Description of the Related Art
With the growth in use of portable electronic devices, the demand for non-volatile memory has increased. Among the various kinds of non-volatile memory, phase change memory is the most competitive next generation non-volatile memory due to its faster speed, lower power consumption, higher capacity, reliability, easier process integration and lower cost.
The SET and RESET operations are mainly achieved by inputting two current pulses with different current magnitudes to the phase change memory to switch the phase change memory between an amorphous state and a crystalline state. According to Ohm's Law, when the current is input to the phase change memory, the phase change memory is heated. The phase change memory may thus be crystallized or fused based on different currents. Based on the described, the logic state of the phase change memory can be switched by inputting different currents, enabling data storage. FIG. 1 is a schematic diagram showing the writing current pulse and the reading current pulse Iread of the phase change memory. When a RESET operation is applied to the phase change memory, a reset current IRESET with high amplitude and short duration is applied, the phase change memory is thus fused because the temperature of the phase change memory exceeds the fusion temperature of the phase change material of the phase change memory. When the temperature of the phase change memory decreases, the state of the phase change memory is transformed to the amorphous state due to an insufficient cool down period. Thus the phase change memory has high resistance. When a SET operation is applied to the phase change memory, a set current ISET with lower amplitude and longer duration is applied. The phase change memory is heated by the set current ISET, and the temperature of the phase change memory is held substantially between the fusion temperature and a crystallizing temperature of the phase change material used by the phase change memory. During the SET operation, the fused phase change memory has sufficient time for crystallizing and the phase change memory thus has low resistance.
FIG. 2 is a schematic diagram of a conventional SET signal for the phase change memory. The SET signal comprises a first crystallizing current pulse ISET1 and a second crystallizing current pulse ISET2. The first crystallizing current pulse ISET1 has a first peak current and the duration time of the first peak current IP1 is a first time period t1. The second crystallizing current pulse ISET2 has a second peak current IP2 and the duration time of the second peak current is a second time period t2.
The conventional SET signal is generated by combining two current pulses with different peak currents, and the conventional SET operation is achieved by inputting a SET signal, such as the SET signal illustrated in FIG. 2, to the phase change memory. When comparing the first crystallizing current pulse ISET1 and the second crystallizing current pulse ISET2, the first peak current is higher than the second peak current, and the first time period is shorter than the second time period. Therefore, when the first crystallizing current pulse ISET1 is input to the phase change memory, the phase change material of the phase change memory is quickly heated, and partial phase change material is crystallized. Then, when the second crystallizing current pulse ISET2 is input to the phase change memory with lower current and longer time, the phase change material is completely crystallized. According to the described operation, reliability and the uniformity of the phase change memory can be improved.
FIG. 3 is a schematic diagram of a current generator outputting the SET signal shown in FIG. 2. The first current generator 31 and the second current generator 32 are coupled to the adder 35 respectively, via a first diode 33 and a second diode 34. The first current generator 31 outputs a first current pulse having an amplitude of (IP1-IP2), and the second current pulse generator outputs a second current pulse having an amplitude of IP2. The first current generator 31 and the second current generator 32 simultaneously output the first current pulse and the second current pulse for a duration time t1 based on the control signals S1 and S2. Then, the control signal S1 disables the first current generator 31 to stop outputting the first current pulse and the second control signal S2 controls the second current generator 32 to output the second current pulse for a duration time t2. According to the described operation, the SET signal illustrated in FIG. 2 can be generated.